Pre-Release 2𝝁𝒎 bRRAM Process!
Date: 7/10/2026
We are excited to announce the pre-release of the 2 micrometer bRRAM Process.
Engineered to support heterogeneous integration on Silicon CMOS processes, this new bulk resistive random-access memory (bRRAM) capability enables design acceleration and system integration across a variety of next-generation architectures. It provides a reliable platform for embedded memory, near- or in-memory computing, neuromorphic computing, and in-sensor computing. For complete technical specifics, please refer to the file UCSD 2um bRRAM Process Info Sheet.
Advanced Material Stack: Features a 64-level resistive memory technology built upon Al2O3/TiOx switching stack.
Filament-Free Switching: Employs area-type, bulk switching mechanisms with no filament formation.
Low Thermal Budget: Fabricated using a low-temperature (350°C) process compatible with standard backend CMOS integration.
Flexible Test Configurations: Supports single-cell test chips as well as array configurations including 2×2, 3×3, 16×16, 32×32.
Comprehensive EDA Tool Support: Fully integrated within AWR and ADS pipelines, offering a dedicated PDK with Virtuoso, SPICE models, reference designs, and library cells.
Substrate & Reliability: Provides 4″ wafer process capability and is environmentally stabilized via SiO2 passivation.
| Parameter | UCSD bRRAM 2µm Target Value |
| Vset/reset | +2 – 3.5 V |
| Resistance Range | ± 10-100MΩ |
| Pulse Width | ~10 µs – 100 ms |
| Switching | Area-type |
| Endurance | >10^6
|
| Retention | ~2.5 years @ 25°C |
| Cell Structure | 1R |
| Selector | None |